The present invention relates to a display device, and more particular, to a display device making use of a flat-surface type display panel, and is suited to a circuit substrate that supplies a signal and a voltage required for driving of a display panel.
Display devices of various types such as liquid crystal display devices making use of a liquid crystal panel as a display panel, which constitutes a highly-accurate flat-surface type display device capable of color display for portable telephones, note-sized computers, or display monitors, organic electroluminescence display devices (organic EL display devices), field emission type display devices (FED), plasma display devices, or the like have already come into practical use, or are in the study phase of commercial application.
In particular, high accuracy and lightening are greatly demanded of display devices used for portable telephones in recent years. Display devices of this type propagate as a display module, in which a backlight, a drive circuit, a peripheral circuit, etc. are incorporated into a display panel such as liquid crystal panel, etc. In, for example, display modules for portable telephones, various signals and voltages for display are supplied to a drive circuit chip, which is mounted on a substrate of a display panel, from a signal processing circuit substrate with the use of a flexible printed circuit substrate (FPC). In addition, while the invention is not limited to FPC but is also applicable to a so-called printed circuit substrate, it is described here taking a FPC as a typical example.
Such circuit substrates called FPC mount solder mounted parts such as resistors, capacitors, etc. and comprise an insulating substrate made of base film, a conductive layer of copper or the like to constitute a wiring pattern, an insulating layer to cover a part of the conductive layer, and a plating layer applied to that portion of the conductive layer, which is exposed from the insulating layer. Solder resist (insulating layer), which serves to avoid adherence of a plating layer to portions except a necessary conductive layer, is coated or stuck to a region, in which solder mounted parts are mounted. An opening is formed in the solder resist and terminals of parts being mounted are solder-connected to wiring terminals exposed from the opening.
FIGS. 12A and 12B are views illustrating misalignment between an opening of solder resist and a conductive layer in a conventional FPC, FIG. 12A being a cross sectional view, and FIG. 12B being a plan view. In FIGS. 12A and 12B, upper sections illustrate the case where there is no misalignment between an opening of solder resist and a conductive layer, and lower sections illustrate the case where there is misalignment between the opening of the solder resist SRG and the conductive layer. In FIGS. 12A and 12B, a FPC comprises an insulating substrate BFM made of a base film, a conductive layer (a wiring pattern of copper) CPT, solder resist SRG being an insulating layer to cover a part of the conductive layer CPT, and a gold plating layer APL applied to that portion of the conductive layer CPT, which is exposed from the solder resist SRG. FIG. 12A shows a laminated state of the elements, and FIG. 12B shows an opening of the solder resist SRG and a state of misalignment in a plane of the opening.
In the case where there is no misalignment between the opening of the solder resist and the conductive layer, the gold plating layer APL is correctly formed on the conductive layer (a wiring pattern of copper) CPT within the opening of the solder resist, as shown in the upper sections of FIGS. 12A and 12B. In contrast, in the case where there is misalignment S of at least ΔS between the opening of the solder resist and the conductive layer, there comes out a state, in which the gold plating layer APL formed on the conductive layer (a wiring pattern of copper) CPT becomes narrow within the opening of the solder resist SRG and the insulating substrate BFM made of a base film is exposed to a A region, as shown in the lower sections of FIGS. 12A and 12B. When electronic parts are mounted in such state, there occurs a state, in which terminals of the electronic parts are not connected normally to the gold plating layer APL formed on the conductive layer CPT.
Shift of an opening of solder resist formed on a FPC from a normal position is prescribed to be, for example, at most 0.1 mm while being according to a degree of minuteness of a wiring pattern. Conventionally, an amount of misalignment of a solder resist opening is visually inspected with the use of a microscope of about 10 magnifications.